Based on silicon metal oxide semiconductor field effect transistor (Si MOSFET) transistor scaling and the so-called research roadmap, the 15 nm node (physical gate length, <7 nm) of Si complementary metal oxide semiconductor (CMOS) will reach a fundamental limitation and will have no significant performance advancement over the larger 22 nm node version due to limitations of mobility and sheet carrier density. To improve the n-MOSFET performance beyond the 15 nm node requires an electron mobility >2000 cm2N-s with a sheet electron density >8×1012 cm−2. Silicon researchers have employed strain in the Si and SiGe channel for mobility enhancement as well as non-planar double gate (FINFET) and non-planar tri-gate methods for sheet carrier improvement. However, all the above mentioned methods of enhancement have failed to meet the requirement of a 15 nm Si CMOS node.
The field effect transistor (FET) is a majority carrier device transferring carriers (typically electrons) from a source to a drain with an applied gate voltage on a reverse-biased junction (between source and drain) modulating the conductivity of the source-to-drain FET channel. Fundamental FET operation is based on the ability of the capacitance charging and discharging process on the gate determining the channel modulation speed.
For example, FIG. 1 represents a MOSFET with gate scaling (lateral size) below 20 nm and an oxide thickness under the gate smaller (thinner) than 5 nm. There are numerous issues and limitations concerning the FET, related to breakdown voltage, output conductance, and gate leakage current due to tunneling through the thin gate oxide.
It is among the objects of the present invention to provide solution to the above-describe types of prior art problems and limitations, and to provide improved transistor devices and techniques.